This application claims priority from Korean patent application No. 2002-45693 filed Aug. 1, 2002, and incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of accurately reading data and an associated data read method.
2. Description of Related Art
In a double data rate (DDR) semiconductor memory device, an on time control and latch clock signals are generated responsive to an internal clock signal internally generated by a delay locked loop. The on time control signal controls a data output buffer. The latch clock signal determines data latching times are generate.
In a conventional DDR device, the data output buffer latches and outputs data only when the latch clock signal is generated after the on time control signal.
When the conventional DDR device operates at low frequency, the data output buffer properly outputs the data because the on time control signal is generated before the latch clock signal. In contrast, when the DDR device operates at high frequency, the data output buffer does not correctly output the data (e.g., data might be delayed) because the latch clock signal is generated before the on time control signal.
The on time control signal is generated before the latch clock signal during high frequency operation because the on time control signal is generated at a constant frequency without depending on the operating frequency of the semiconductor memory device. The latch clock signal, on the other hand, is generated responsive to the operating frequency of the semiconductor memory device. Accordingly, the latch clock signal might be inadvertently generated before the on time signal where the device operates in high frequency.
FIG. 1 is a block diagram of a data read path in a conventional DDR semiconductor memory device. The conventional DDR device includes a first and a second data banks 10-1 and 10-2, sense amplifiers 12-1 and 12-2, data output buffers 14-1 and 14-2, a data output driver 16, a delay locked loop 20, a latch clock signal CLKDQF, CLFDQS generating circuit 24, a clock signal (CLK2F CLK2S) generating circuit 22, a latency signal (LAB) generating circuit 26, an on time control signal (PTRSTF, PTRSTS) generating circuit 28, and a mode setting circuit 30.
The first memory bank 10-1 reads and writes data responsive to rising edge of a clock signal. The second memory bank 10-2 reads and writes data responsive to the falling edge of the clock signal (not shown).
The sense amplifier 12-1 amplifies the data read out from the first memory bank 10-1 and the sense amplifier 12-2 amplifies the data read out from the second memory bank 10-2.
The data output buffer 14-1 receives an output signal of the sense amplifier 12-1 responsive to the on time control signal PTRSTF, and then buffers and outputs the received signal responsive to the latch clock signal CLKDQF. The data output buffer 14-2 receives an output signal of the sense amplifier 12-2 responsive to the on time control signal PTRSTF, and then buffers and outputs the received signal responsive to the latch clock signal CLKDQS.
The delay locked loop 20 receives the clock signal CLK and generates the clock signals CLK1F, CLK1S.
The clock signal generating circuit 2 receives the clock signals CLK1F and CLK1S and generates clock signals CLK2F and CLK2S. The latch clock signal generating circuit 24 generates the latch clock signals CLKDQF and CLKDQS responsive to the clock signals CLK1F, CLK1S and the column address strobe (CAS) latency signals CL1.5, CL2, CL2.5, CL3.
The latency signal generating circuit 26 generates a latency signal LAB responsive to the CAS latency signals CL1.5, CL2, CL2.5 and CL3 and the clock signals CLK2F and CLK2S.
The on time control signal generating circuit 28 receives the latency signal LAB responsive to the clock signals CLK2F, CLK2S and generates the on time control signals PTRSTF, PTRSTS.
The mode setting circuit 30 receives the CAS latency signals CL1.5, CL2, CL2.5 and CL3 input from address pins (not shown) during a mode setting operation.
FIG. 2 is a circuit diagram of a data output buffer embodiment. The conventional data output buffer comprises a data output buffer 14-1 including an input circuit 14-11 and a buffer/latch circuit 14-12, and a data output buffer 14-2 including an input circuit 14-2 and a buffer/latch circuit 14-22.
The input circuit 14-11 comprises an inverter I1, a NOR gate NOR1 and a NAND gate NA1. The buffer/latch circuit 14-12 comprises an inverter I3, NAND gates NA2 and NA3, NOR gates NOR2 and NOR3, PMOS transistors P1 and P2, NMOS transistors N1 and N2 and a latch L1 comprising inverters I5 and I6.
The input circuit 14-21 comprises an inverter I2, a NOR gate NOR4, and a NAND gate NA4. The buffer/latch circuit 14-22 comprises an inverter I4, NAND gates NA5 and NA6, NOR gates NOR5 and NOR6, PMOS transistors P3 and P4, NMOS transistors N3 and N4, and a latch L2 comprising I7 and I8.
The data output buffers 14-1 and 14-2, each buffer one bit of data DOF or DOS. The data output buffer 14-1 operates as we describe below. The data output buffer 14-2 operates similarly to data output buffer 14-1. T
When the on time control signal PTRSTF is at a logic xe2x80x9chighxe2x80x9d level is, the NOR gate NOR1 and the NAND gate NA1 invert the data DOF. That is, if the data DOF is at a logic xe2x80x9chighxe2x80x9d level, the NOR gate NOR1 and the NAND gate NA1 output the data DOF at a of logic xe2x80x9clowxe2x80x9d level. The NAND gates NA2 and NA3 generate logic xe2x80x9chighxe2x80x9d level signals. Accordingly, the PMOS transistors P1 and P2 are turned off. At this time, if the clock signal CLKDQF has the logic xe2x80x9chighxe2x80x9d level, the NOR gates NOR2 and NOR3 generate corresponding logic xe2x80x9chighxe2x80x9d level signals. Accordingly, the NMOS transistors N1 and N2 are turned on and thus logic xe2x80x9clowxe2x80x9d level signals are generated at a common node of the PMOS transistor P1 and the NMOS transistor N1 and a common node of the PMOS transistor P2 and the NMOS transistor N2. The latches L1 and L2 invert and latch the logic xe2x80x9clowxe2x80x9d level signal, and then generate signals DOP and DON having logic xe2x80x9chighxe2x80x9d levels. On the other hand, if the clock signal CLKDQF has logic xe2x80x9clowxe2x80x9d level, the NAND gates NA2 and NA3 generate corresponding logic xe2x80x9chighxe2x80x9d level signals and the NOR gates NOR2 and NOR3 generate corresponding logic xe2x80x9clowxe2x80x9d level signals. Accordingly, the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 are turned off, and the latches L1 and L2 output the previously latched signals as the data DOP and DON.
On the other hand, when the on time control signal PTRSTF has a logic xe2x80x9clowxe2x80x9d level, the NOR gate NOR1 generates a logic xe2x80x9clowxe2x80x9d level signal and the NAND gate NA1 generates a logic xe2x80x9chighxe2x80x9d level signal. The NAND gate NA2 generates a logic xe2x80x9chighxe2x80x9d level signal and the NOR gate NOR3 generates a logic xe2x80x9clowxe2x80x9d level signal. Accordingly, the PMOS transistor P1 and the NMOS transistor N2 are turned off. If the clock signal CLKDQF has the logic xe2x80x9clowxe2x80x9d level, the NOR gate NOR2 generates a logic xe2x80x9clowxe2x80x9d level signal and the NAND gate NA3 generates a logic xe2x80x9chighxe2x80x9d level signal. Accordingly, the NMOS transistor N1 and the PMOS transistor P2 are turned off. The latches L1 and L2 output the latched data DOP and DON, respectively.
As described above, the data output buffer buffers and latches the data DOF and outputs the data DOP and DON.
When the on time control signal PTRSTF is at a logic xe2x80x9clowxe2x80x9d and the clock signal CLKDQF of the logic xe2x80x9chighxe2x80x9d level is applied, the NOR gate NOR1 outputs the logic xe2x80x9clowxe2x80x9d level signal and the NAND gate NA1 outputs the logic xe2x80x9chighxe2x80x9d level signal, so that the NAND gate NA2 generates logic xe2x80x9chighxe2x80x9d level signal and the NOR gate NOR3 generates the logic xe2x80x9clowxe2x80x9d level signal. Further, the NOR gate NOR2 generates the logic xe2x80x9chighxe2x80x9d level signal and the NAND gate NA3 generates the logic xe2x80x9clowxe2x80x9d level signal. Accordingly, the NMOS transistor N1 and the PMOS transistor P2 are turned on, and the latches L1 and L2 invert and latch the logic xe2x80x9clowxe2x80x9d level signal and the logic xe2x80x9chighxe2x80x9d level signal, respectively, thereby outputting the data DOP having logic xe2x80x9chighxe2x80x9d level and the data DON having logic xe2x80x9clowxe2x80x9d level.
Accordingly, if the clock signal CLKDQF is transited to a logic xe2x80x9chighxe2x80x9d level before the on time control signal PTRSTF is transited to logic xe2x80x9chighxe2x80x9d level, the data DOP of logic xe2x80x9chighxe2x80x9d level and the data DON of logic xe2x80x9clowxe2x80x9d level are generated. Thus, the data output driver in FIG. 1 generates an output signal of high impedance state.
Therefore, if the on time clock signal PTRSTF is generated after the clock signal, the data DOF may be belatedly output or may not be output at all. Accordingly, it is necessary that the on time clock signal be generated before the clock signal is generated to output the data correctly.
FIG. 3 illustrates a circuit diagram of an example of the clock signal generating circuit 22 in FIG. 1. The clock signal generating circuit 22 comprises an inverter I9, a delay circuit 40 comprising inverters I10-I5, NAND gates NA7, NA8 and a delay circuit 42 comprising of inverters I16, I17, I18.
Operation of the clock signal generating circuit is as follows.
The inverter I9 inverts the clock signal CLK1. The delay circuit 40 delays an output signal of the inverter I9. The NAND gate NA7 logically NANDs the output signal of the inverter I9 and an output signal of the delay circuit 40. The NAND gate NA8 generates the clock signal CLK2 by logically NANDing the output signal of the inverter I9 and an output signal of the NAND gate NA7. The delay circuit 42 inverts and delays an output signal of the NAND gate NA8. That is, the inverter I9, the delay circuit 40 and the NAND gates NA7, NA8 in FIG. 3 detects a falling edge of the clock signal CLK1 and generates the clock signal CLK2. The delay circuit 42 inverts and delays the output signal of the NAND gate NA8.
FIG. 4A is a timing diagram of the semiconductor memory device shown in FIG. 1. In FIG. 4A, the CAS latency signal CL3 is 1, a burst length is 4, the clock signal has a high frequency, and a read command is input at a rising edge of a clock signal CLK.
The delay locked loop 20 receives the clock signal CLK as an input and generates the clock signals CLK1F, CLK1S. The clock signal CLK2F, CLK2S generating circuit 22 detects falling edges of the clock signals CLK1F, CLK1S and generates the clock signals CLK2F, CLK2S, respectively. The latency signal generating circuit 26 generates the latency signal LAB responsive to a rising edge of a third clock of the clock signal CLK2F. The on time control signal generating circuit 28 generates the on time clock signals PTRSTF, PTRSTS responsive to the latency signal LAB and the clock signals CLK2F, CLK2S. The latch clock signal generating circuit 24 generates the latch clock signals CLKDQF, CLKDQS responsive to the clock signals CLK1F, CLK1S and the latency signals CL1.5, CL2, CL2.5, CL3.
When the semiconductor memory device is operates with a CAS latency of 3 or greater (that is, the device operates at a high frequency), generation of the on time control signals PTRSTF, PTRSTS is delayed, delaying the generation of on time control signals PTRSTF, PTRSTS to a time T1 after the latch clock signals CLKDQF, CLKDQS are generated. Accordingly, a first and second data DOUT1, DOUT2 are also delayed. Further, if the on time control signals PTRSTF, PTRSTS are generated deviating from the logic xe2x80x9chighxe2x80x9d level of the first latch clock signals CLKDQF, CLKDQS, the first and second data DOUT1, DOUT2 may not be output. The semiconductor memory device with a CAS latency of less than 3 operates at a low frequency.
FIG. 4B is a timing diagram of the semiconductor memory device shown in FIG. 1. In FIG. 4B, the CAS latency signal CL3 is 1, a burst length is 4, the clock signal has a low frequency and a read command is input at the rising edge of the clock signal CLK. Under these circumstances, the on the control signals PTRSTF, PTRSTS are generated before than the latch clock signals CLKDQF, CLKDQS by a time T2. Accordingly, the data DOUT1, DOUT2, DOUT3, DOUT4 are accurately output.
As shown in FIGS. 4A and 4B, when the semiconductor memory device operates at high frequency, the on time control signals PTRSTF, PTRSTS are generated before the latch clock signals CLKDQF, CLKDQS. Accordingly, the latch clock signals CLKDQF, CLKDQS are generated before the on time control signals PTRSTF, PTRSTS. These conditions delay the data read time and produce erroneous output results.
Where the CAS latency is 3, the semiconductor memory device does not generally operate at a low frequency as shown in FIG. 4B. The timing diagram of FIG. 4B, however, shows that generation of the latch clock signals occurs earlier than generation of the on time control signal with an increase in frequency.
An object of the present invention is to overcome disadvantages associated with reading prior semiconductor memory devices.
Another object of the present invention is to provide a semiconductor memory device capable of reading data precisely and correctly.
Yet another object of the present invention is to provide a method for reading data precisely and correctly from a semiconductor memory device. A semiconductor memory device includes a data output buffer adapted to receive input data responsive to an on time control signal and adapted to buffer the input data responsive to a latch clock signal. A first clock signal generating means is adapted to generate a first clock signal responsive to a reference signal. A second clock signal generating means is adapted to generate a second clock signal responsive to the first clock signal and a mode signal. A latency signal generating means is adapted to generate a latency signal responsive to the mode signal. A latch clock generating means adapted to generate the latch clock signal responsive to the second clock signal and the mode signal. And an on time control signal generating means adapted to generate the on time control signal responsive to the second clock signal and the latency signal.
The second clock signal generating means is adapted to generate the second clock signal responsive to a falling edge of the first clock signal when the device operates at low frequency. And the second clock signal generating means is adapted to generate the second clock signal by buffering and delaying the first clock signal when the device operates at high frequency.
The second clock signal generating means is adapted to operate differently when the device operates at a low frequency than when the device operates at a high frequency. The second clock generating means includes a pulse signal generating means adapted to generate a pulse signal responsive to a falling edge of the first clock signal. A first delay means is adapted to generate a first delay signal by delaying the first clock signal by a first predetermined time. A switching means is adapted to generate a switching signal by transmitting the pulse signal when the device operates at low frequency or the delayed first clock signal when the device operates at high frequency. And a second delay means is adapted to delay the switching signal by a second predetermined time.
The pulse signal generating means includes an inverting means adapted to generated an inverted first clock signal by inverting the first clock signal. A third delay means is adapted to generate a delayed inverted first clock signal by delaying the inverted first clock signal by a predetermined third time. A first logic means is adapted to generate a first logic signal by logically manipulating the delayed inverted first clock signal and the inverted first clock signal. And a second logic means is adapted to generate a second logic signal by logically manipulating the first logic signal with the inverted first clock signal.
The switching means includes a first transmission gate adapted to transmit the second logic signal responsive to the mode signal. And a second transmission gate is adapted to transmit the first delay signal responsive to the mode signal.
The first and third predetermined times are about equal. And the second predetermined time is longer than the first predetermined time.
A method for reading data from a semiconductor memory device includes generating a first clock signal responsive to an externally applied clock signal, generating a second clock signal responsive to a mode signal, the mode signal indicating whether the device operates at a high or low frequency, generating a latch clock signal responsive to the second clock signal and the mode signal, generating an on time control signal responsive to a latency signal, and reading the data responsive to the second clock signal and the on time control signal.
The method further includes providing a pulse signal when the device operates in the low frequency and providing a delayed signal when the device operates in the high frequency.
The method further includes detecting a falling edge of the first clock signal and buffering and delaying the first clock signal.